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FEATURES Two Fast 12-Bit ADCs Four Input Channels Simultaneous Sampling & Conversion 4 s Throughput Time Single Supply Operation Selection of Input Ranges: 10 V for AD7862-10 2.5 V for AD7862-3 0 V to 2.5 V for AD7862-2 High Speed Parallel Interface Low Power, 60 mW typ Power Saving Mode, 50 W typ Overvoltage Protection on Analog Inputs 14-Bit Pin Compatible Upgrade (AD7863) APPLICATIONS AC Motor Control Uninterrupted Power Supplies Data Acquisition Systems Communications GENERAL DESCRIPTION
Simultaneous Sampling Dual 250 kSPS 12-Bit ADC AD7862
FUNCTIONAL BLOCK DIAGRAM
VREF +2.5V REFERENCE VDD 2k
AD7862
VA1 VB1 VA2 VB2
SIGNAL SCALING SIGNAL SCALING SIGNAL SCALING SIGNAL SCALING
MUX
TRACK/ HOLD
12-BIT ADC OUTPUT LATCH 12-BIT ADC
DB0 DB11
MUX
TRACK/ HOLD
CS CONVERSION CONTROL LOGIC CLOCK RD
A0
BUSY CONVST
AGND
AGND
DGND
The AD7862 is a high speed, low power, dual 12-bit A/D converter that operates from a single +5 V supply. The part contains two 4 s successive approximation ADCs, two track/ hold amplifiers, an internal +2.5 V reference and a high speed parallel interface. There are four analog inputs that are grouped into two channels (A & B) selected by the A0 input. Each channel has two inputs (VA1 & VA2 or VB1 & VB2) that can be sampled and converted simultaneously thus preserving the relative phase information of the signals on both analog inputs. The part accepts an analog input range of 10 V (AD7862-10), 2.5 V (AD7862-3) and 0-2.5 V (AD7862-2). Overvoltage protection on the analog inputs for the part allows the input voltage to go to 17 V, 7 V or +7 V, respectively, without causing damage. A single conversion start signal (CONVST) places both track/ holds into hold simultaneously and initiates conversion on both inputs. The BUSY signal indicates the end of conversion, and at this time the conversion results for both channels are available to be read. The first read after a conversion accesses the result from VA1 or VB1, while the second read accesses the result from VA2 or VB2, depending on whether the multiplexer select A0 is low or high, respectively. Data is read from the part via a 12-bit parallel data bus with standard CS and RD signals. In addition to the traditional dc accuracy specifications such as linearity, full-scale and offset errors, the part is also specified for dynamic performance parameters including harmonic distortion and signal-to-noise ratio. REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
The AD7862 is fabricated in Analog Devices' Linear Compatible CMOS (LC2MOS) process, a mixed technology process that combines precision bipolar circuits with low power CMOS logic. It is available in 28-lead SSOP, SOIC and DIP.
PRODUCT HIGHLIGHTS
1. The AD7862 features two complete ADC functions allowing simultaneous sampling and conversion of two channels. Each ADC has a 2-channel input mux. The conversion result for both channels is available 3.6 s after initiating conversion. 2. The AD7862 operates from a single +5 V supply and consumes 60 mW typ. The automatic power-down mode, where the part goes into power down once conversion is complete and "wakes up" before the next conversion cycle, makes the AD7862 ideal for battery-powered or portable applications. 3. The part offers a high speed parallel interface for easy connection to microprocessors, microcontrollers and digital signal processors. 4. The part is offered in three versions with different analog input ranges. The AD7862-10 offers the standard industrial input range of 10 V; the AD7862-3 offers the common signal processing input range of 2.5 V; while the AD7862-2 can be used in unipolar 0 V - +2.5 V applications. 5. The part features very tight aperture delay matching between the two input sample-and-hold amplifiers.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 (c) Analog Devices, Inc., 1996
AD7862-SPECIFICATIONS (V = +5 V 5%, AGND = DGND = 0 V, REF = Internal. All Specifications T unless otherwise noted.)
DD
MIN
to TMAX
Parameter SAMPLE AND HOLD -3 dB Small Signal Bandwidth Aperture Delay Aperture Jitter Aperture Delay Matching DYNAMIC PERFORMANCE2 Signal to (Noise+Distortion) Ratio3 @ +25C TMIN to TMAX Total Harmonic Distortion3 Peak Harmonic or Spurious Noise3 Intermodulation Distortion3 2nd Order Terms 3rd Order Terms Channel to Channel Isolation3 DC ACCURACY Resolution Minimum Resolution for which No Missing Codes are Guaranteed Relative Accuracy3 Differential Nonlinearity3 Positive Gain Error3 Positive Gain Error Match3 AD7862-10 Negative Gain Error3 Bipolar Zero Error Bipolar Zero Error Match AD7862-3 Negative Gain Error3 Bipolar Zero Error Bipolar Zero Error Match AD7862-2 Unipolar Offset Error Unipolar Offset Error Match ANALOG INPUTS AD7862-10 Input Voltage Range Input Resistance AD7862-3 Input Voltage Range Input Resistance AD7862-2 Input Voltage Range Input Current REFERENCE INPUT/OUTPUT REF IN Input Voltage Range REF IN Input Capacitance4 REF OUT Output Voltage REF OUT Error @ +25C REF OUT Error TMIN to TMAX REF OUT Temperature Coefficient REF OUT Output Impedance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN4
A Version1 3 20 100 200
B Version 3 20 100 200
S Version 3 20 100 200
Units MHz typ ns typ ps typ ps typ
Test Conditions/Comments
fIN = 100.0 kHz, fS = 250 kSPS 70 70 -78 -85 -85 -85 -80 12 12 1 1 4 4 4 4 4 4 4 4 +4 4 71 70 -78 -85 -85 -85 -80 12 12 1 1 3 3 3 3 3 3 3 3 +3 3.5 70 70 -78 -85 -85 -85 -80 12 12 1 1 4 4 4 4 4 4 4 4 +4 4 dB min dB min dB max dB typ fa = 49 kHz, fb = 50 kHz dB typ dB typ dB max Bits Bits LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max Typically 0.4 LSB fIN = 100 kHz Sine Wave Any Channel
10 24 2.5 6 +2.5 500 2.375/2.625 10 2.5 10 25 25 2 2.4 0.8 10 10
10 24 2.5 6 +2.5 500 2.375/2.625 10 2.5 10 25 25 2 2.4 0.8 10 10
10 24 2.5 6 +2.5 500 2.375/2.625 10 2.5 10 25 25 2 2.4 0.8 10 10
Volts k min Volts k min Volts nA max
Input Input Input
V min/V max 2.5 V 5% pF max V nom mV max mV max ppm/C typ k nom V min V max A max pF max VDD = 5 V 5% VDD = 5 V 5%
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AD7862
Parameter LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL DB11-DB0 Floating-State Leakage Current Floating-State Capacitance4 Output Coding AD7862-10, AD7862-3 AD7863-2 CONVERSION RATE Conversion Time Track/Hold Acquisition Time2, 3 POWER REQUIREMENTS VDD IDD Normal Mode Standby Mode Power Dissipation Normal Mode Standby Mode A Version1 4.0 0.4 10 10 B Version 4.0 0.4 10 10 S Version 4.0 0.4 10 10 Units V min V max A max pF max Twos Complement Straight (Natural) Binary 3.6 0.3 +5 15 25 75 125 3.6 0.3 +5 15 25 75 125
4
Test Conditions/Comments ISOURCE = 200 A ISINK = 1.6 mA
3.6 0.3 +5 15 25 75 125
s max s max V nom mA max A max mW max W max
For Both Channels
5% for Specified Performance
Logic Inputs = 0 V or VDD Typically 60 mW Typically 75 W
NOTES 1 Temperature ranges are as follows: A, B Versions: -40C to +85C; S Version: -55C to +125C. 2 Performance measured through full channel (multiplexer, SHA and ADC). 3 See Terminology.
Sample tested @ +25C to ensure compliance.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
(TA = +25C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V Analog Input Voltage to AGND AD7862-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 V AD7862-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V AD7862-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V Reference Input Voltage to AGND . . . -0.3 V to VDD + 0.3 V Digital Input Voltage to DGND . . . . . -0.3 V to VDD + 0.3 V Digital Output Voltage to DGND . . . . -0.3 V to VDD + 0.3 V Operating Temperature Range Commercial (A, B Version) . . . . . . . . . . . -40C to +85C Extended (S Version) . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150C Plastic DIP Package, Power Dissipation . . . . . . . . . . 670 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 116C/W
Lead Temperature, (Soldering 10 sec) . . . . . . . . . . +260C Ceramic DIP Package, Power Dissipation . . . . . . . . . 670 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 116C/W Lead Temperature, (Soldering 10 sec) . . . . . . . . . . +260C SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 110C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220C SSOP Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 110C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220C
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model AD7862AR-10 AD7862BR-10 AD7862ARS-10 AD7862AN-10 AD7862SQ-10 AD7862AR-3 AD7862BR-3 AD7862ARS-3 AD7862AN-3 AD7862AR-2 AD7862ARS-2 REV. 0
Input Input 10 V 10 V 10 V 10 V 10 V 2.5 V 2.5 V 2.5 V 2.5 V 0 V to 2.5 V 0 V to 2.5 V
Relative Accuracy 1 LSB 1 LSB 1 LSB 1 LSB 1 LSB 1 LSB 1 LSB 1 LSB 1 LSB 1 LSB 1 LSB
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -3-
Package Description 28-Bit Small Outline Package 28-Bit Small Outline Package 28-Bit Shrink Small Outline Package 28-Bit Plastic DIP 28-Bit Cerdip 28-Bit Small Outline Package 28-Bit Small Outline Package 28-Bit Shrink Small Outline Package 28-Plastic DIP 28-Bit Small Outline Package 28-Bit Shrink Small Outline Package
Package Option R-28 R-28 RS-28 N-28 Q-28 R-28 R-28 RS-28 N-28 R-28 RS-28
AD7862 TIMING CHARACTERISTICS1, 2
Parameter tCONV tACQ Parallel Interface t1 t2 t3 t4 t5 3 t6 4 t7 A, B Versions 3.6 0.3 0 0 35 35 12 60 5 30 40
(VDD = +5 V 5%, AGND = DGND = 0 V, REF = Internal. All Specifications TMIN to TMAX unless otherwise noted.)
S Version 3.6 0.3 0 0 45 45 12 70 5 40 40 Units s max us max ns min ns min ns min ns min ns min ns max ns min ns max ns min Test Conditions/Comments Conversion Time Acquisition Time CS to RD Setup Time CS to RD Hold Time CONVST Pulse Width Read Pulse Width Data Access Time After Falling Edge of RD Bus Relinquish Time After Rising Edge of RD Time Between Consecutive Reads
NOTES 1 Sample tested at +25C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.6 V. 2 See Figure 1. 3 Measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8 V or 2.0 V. 4 These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances. Specifications subject to change without notice.
CONVST
t3
BUSY
tCONV
A0
CS
.........
t1 t2 t4 t5 t6
VA1 VA2 VB1
.........
t7
RD
DATA
VB2
Figure 1. Timing Diagram
1.6mA
TO OUTPUT PIN 50pF 200A
+1.6V
Figure 2. Load Circuit for Access Time and Bus Relinquish Time
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7862 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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AD7862
PIN FUNCTION DESCRIPTION
Pin 1 2 3-6 7 8 9-15 16 17 18 19
Mnemonic NC DB11 DB10-DB7 DGND CONVST DB6-DB0 AGND VB2 VA2 VREF
Description No Connect Data Bit 11 (MSB). Three-state TTL output. Output coding is twos complement for the AD786210 and AD7862-3. Output coding is straight (natural) binary for the AD7862-2. Data Bit 10 to Data Bit 7. Three-state TTL outputs. Digital Ground. Ground reference for digital circuitry. Convert Start Input. Logic Input. A high to low transition on this input puts both track/holds into their hold mode and starts conversion on both channels. Data Bit 6 to Data Bit 0. Three-state TTL outputs. Analog Ground. Ground reference for mux, track/hold, reference and DAC circuitry. Input Number 2 of Channel B. Analog Input voltage ranges of 10 V (AD7862-10), 2.5 V (AD7862-3) and 0 V-2.5 V (AD7862-2). Input Number 2 of Channel A. Analog Input voltage ranges of 10 V (AD7862-10), 2.5 V (AD7862-3) and 0 V-2.5 V (AD7862-2). Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the output reference source for the analog-to-digital converter. The nominal reference voltage is 2.5 V, and this appears at the pin. Multiplexer Select. This input is used in conjunction with RD and CS low to enable the data outputs. With A0 logic low, one read after a conversion will read the data from each of the ADCs in the sequence, VA1, VA2, and a subsequent read, when A0 goes high, reads the data from VB1, VB2. Chip Select Input. Active low logic input. The device is selected when this input is active. Read Input. Active low logic input. This input is used in conjunction with A0 and CS low to enable the data outputs. With A0 logic low, one read after a conversion will read the data from each of the ADCs in the sequence, VA1, VA2, and a subsequent read, when A0 goes high, reads the data from VB1, VB2. Busy Output. The busy output is triggered high by the falling edge of CONVST and remains high until conversion is completed. Analog and Digital Positive Supply Voltage, +5.0 V 5%. Input Number 1 of Channel A. Analog Input voltage ranges of 10 V (AD7862-10), 2.5 V (AD7862-3) and 0 V-2.5 V (AD7862-2). Input Number 1 of Channel B. Analog Input voltage ranges of 10 V (AD7862-10), 2.5 V (AD7862-3) and 0 V-2.5 V (AD7862-2). Analog Ground. Ground reference for mux, track/hold, reference and DAC circuitry. No Connect
PIN CONFIGURATION
NC 1 DB11 2 DB10 3 DB9 4 DB8 5 DB7 6 28 NC 27 AGND 26 VB1 25 VA1
20
A0
21 22
CS RD
23 24 25 26 27 28
BUSY VDD VA1 VB1 AGND NC
AD7862
24 VDD
TOP VIEW 23 BUSY DGND 7 (Not to Scale) 22 RD CONVST 8 DB6 9 DB5 10 DB4 11 DB3 12 DB2 13 DB1 14 21 CS 20 A0 19 VREF 18 VA2 17 VB2 16 AGND 15 DB0
NC = NO CONNECT
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AD7862
TERMINOLOGY Signal to (Noise + Distortion) Ratio Channel-to-Channel Isolation
This is the measured ratio of signal to (noise + distortion) at the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by: Signal to (Noise + Distortion) = (6.02 N + 1.76) dB Thus for a 12-bit converter, this is 74 dB.
Total Harmonic Distortion
Channel-to-Channel isolation is a measure of the level of crosstalk between channels. It is measured by applying a fullscale 100 kHz sine wave signal to each of the four inputs individually. These, in turn, are individually referenced to the other three channels whose inputs are grounded, and the ADC output is measured to determine the level of crosstalk from the other channel. The figure given is the worst case across all four channels.
Relative Accuracy
Relative accuracy or endpoint nonlinearity is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function.
Differential Nonlinearity
Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7862 it is defined as:
THD ( dB ) = 20 log
2 2 2 2 V2 +V3 +V4 +V5
This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC.
Positive Full-Scale Error
V1
where V1 is the rms amplitude of the fundamental and V2, V3, V4 and V5 are the rms amplitudes of the second through the fifth harmonics.
Peak Harmonic or Spurious Noise
This is the deviation of the last code transition (01 . . . 110 to 01 . . . 111) from the ideal 4 x VREF - 3/2 LSB (AD7862-10 10 V range) or VREF - 3/2 LSB (AD7862-3, 2.5 V range) after the Bipolar Offset Error has been adjusted out.
Positive Full-Scale Error (AD7862-2, 0 V to 2.5 V)
Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor, it will be a noise peak.
Intermodulation Distortion
This is the deviation of the last code transition (01 . . . 110 to 01 . . . 111) from the ideal VREF - 3/2 LSB after the unipolar offset error has been adjusted out.
Bipolar Zero Error (AD7862-10, 10 V, AD7862-3, 2.5 V)
This is the deviation of the midscale transition (all 1s to all 0s) from the ideal AGND - 1/2 LSB.
Unipolar Offset Error (AD7862-2, 0 V to 2.5 V)
This is the deviation of the first code transition (00 . . . 000 to 00 . . . 001) from the ideal AGND + 1/2 LSB.
Negative Full-Scale Error (AD7862-1, 2.5 V) 10 V; AD7862-3,
With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which neither m nor n are equal to zero. For example, the second order terms include (fa + fb) and (fa - fb), while the third order terms include (2 fa + fb), (2 fa - fb), (fa + 2 fb) and (fa - 2 fb). The AD7862 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second and third order terms are of different significance. The second order terms are usually distanced in frequency from the original sine waves, while the third order terms are usually at a frequency close to the input frequencies. As a result, the second and third order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in dBs.
This is the deviation of the first code transition (10 . . . 000 to 10 . . . 001) from the ideal -4 x VREF + 1/2 LSB (AD7862-10 10 V range) or -VREF + 1/2 LSB (AD7862-3, 2.5 V range) after Bipolar Zero Error has been adjusted out.
Track/Hold Acquisition Time
Track/Hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, within 1/2 LSB, after the end of conversion (the point at which the track/hold returns to track mode). It also applies to situations where a change in the selected input channel takes place or where there is a step input change on the input voltage applied to the selected VAX/BX input of the AD7862. It means that the user must wait for the duration of the track/hold acquisition time, after the end of conversion or after a channel change/step input change to VAX/BX, before starting another conversion to ensure that the part operates to specification.
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AD7862
CONVERTER DETAILS
The AD7862 is a high speed, low power, dual 12-bit A/D converter that operates from a single +5 V supply. The part contains two 4 s successive approximation ADCs, two track/ hold amplifiers, an internal +2.5 V reference and a high speed parallel interface. There are four analog inputs that are grouped into two channels (A & B) selected by the A0 input. Each channel has two inputs (VA1 & VA2 or VB1 & VB2) that can be sampled and converted simultaneously thus preserving the relative phase information of the signals on both analog inputs. The part accepts an analog input range of 10 V (AD7862-10), 2.5 V (AD7862-3) and 0 V-2.5 V (AD7862-2). Overvoltage protection on the analog inputs for the part allows the input voltage to go to 17 V, 7 V or +7 V, respectively, without causing damage. The AD7862 has two operating modes, the high sampling mode and the auto sleep mode where the part automatically goes into sleep after the end of conversion. These modes are discussed in more detail in the Timing and Control Section. Conversion is initiated on the AD7862 by pulsing the CONVST input. On the falling edge of CONVST, both on-chip track/ holds are placed into hold simultaneously, and the conversion sequence is started on both channels. The conversion clock for the part is generated internally using a laser-trimmed clock oscillator circuit. The BUSY signal indicates the end of conversion, and at this time the conversion results for both channels are available to be read. The first read after a conversion accesses the result from VA1 or VB1 while the second read accesses the result from VA2 or VB2, depending on whether the multiplexer select A0 is low or high, respectively. Data is read from the part via a 12-bit parallel data bus with standard CS and RD signals. Conversion time for the AD7862 is 3.6 s in the high sampling mode (6 s for the auto sleep mode), and the track/hold acquisition time is 0.3 s. To obtain optimum performance from the part, the read operation should not occur during the conversion or during 300 ns prior to the next conversion. This allows the part to operate at throughput rates up to 250 kHz and achieve data sheet specifications.
Track/Hold Section
The acquisition time of the track/hold amplifiers begins at this point.
Reference Section
The AD7862 contains a single reference pin, labelled VREF, which either provides access to the part's own +2.5 V reference or to which an external +2.5 V reference can be connected to provide the reference source for the part. The part is specified with a +2.5 V reference voltage. Errors in the reference source will result in gain errors in the AD7862's transfer function and will add to the specified full-scale errors on the part. On the AD7862-10 and the AD7862-3, it will also result in an offset error injected in the attenuator stage. The AD7862 contains an on-chip +2.5 V reference. To use this reference as the reference source for the AD7862, simply connect a 0.1 F disc ceramic capacitor from the VREF pin to AGND. The voltage that appears at this pin is internally buffered before being applied to the ADC. If this reference is required for use external to the AD7862, it should be buffered as the part has a FET switch in series with the reference output, resulting in a source impedance for this output of 3 k nominal. The tolerance on the internal reference is 10 mV at 25C with a typical temperature coefficient of 25 ppm/C and a maximum error over temperature of 25 mV. If the application requires a reference with a tighter tolerance or the AD7862 needs to be used with a system reference, the user has the option of connecting an external reference to this VREF pin. The external reference will effectively overdrive the internal reference and provide the reference source for the ADC. The reference input is buffered before being applied to the ADC with the maximum input current of 100 A. Suitable reference sources for the AD7862 include the AD680, AD780 and REF43 precision +2.5 V references.
CIRCUIT DESCRIPTION Analog Input Section
The AD7862 is offered as three part types; the AD7862-10, which handles a 10 V input voltage range; the AD7862-3, which handles input voltage range 2.5 V; and the AD7862-2, which handles a 0 V to +2.5 V input voltage range.
+2.5V REFERENCE 2k VREF TO ADC REFERENCE CIRCUITRY R2 R1 VAX R3 AGND MUX TRACK/ HOLD TO INTERNAL COMPARATOR
The track/hold amplifiers on the AD7862 allow the ADCs to accurately convert an input sine wave of full-scale amplitude to 12-bit accuracy. The input bandwidth of the track/hold is greater than the Nyquist rate of the ADC even when the ADC is operated at its maximum throughput rate of 250 kHz (i.e., the track/hold can handle input frequencies in excess of 125 kHz). The track/hold amplifiers acquire input signals to 12-bit accuracy in less than 400 ns. The operation of the track/holds is essentially transparent to the user. The two track/hold amplifiers sample their respective input channels simultaneously on the falling edge of CONVST. The aperture time for the track/holds (i.e., the delay time between the external CONVST signal and the track/hold actually going into hold) is typically 15 ns and, more importantly, is well matched across the two track/holds on one device and also well matched from device to device. This allows the relative phase information between different input channels to be accurately preserved. It also allows multiple AD7862s to sample more than two channels simultaneously. At the end of conversion, the part returns to its tracking mode.
AD7862-10/AD7862-3
Figure 3. AD7862-10/-3 Analog Input Structure
Figure 3 shows the analog input section for the AD7862-10 and AD7862-3. The analog input range of the AD7862-10 is 10 V into an input resistance of typically 33 k. The analog input range of the AD7862-3 is 2.5 V into an input resistance of typically 12 k. This input is benign with no dynamic charging
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AD7862
currents, as the resistor stage is followed by a high input impedance stage of the track/hold amplifier. For the AD7862-10, R1 = 30 k, R2 = 7.5 k, and R3 = 10 k. For the AD7862-3, R1 = R2 = 6.5 k and R3 is open circuit. For the AD7862-10 and AD7862-3, the designed code transitions occur on successive integer LSB values (i.e., 1 LSB, 2 LSBs, 3 LSBs . . .). Output coding is twos complement binary with 1 LSB = FS/4096. The ideal input/output transfer function for the AD7862-10 and AD7862-3 is shown in Table I.
Table I. Ideal Input/Output Code Table for the AD7862-10/-3
applications, offset and full-scale error will have to be adjusted to zero. Figure 4 shows a circuit that can be used to adjust the offset and full-scale errors on the AD7862 (VA1 on the AD7862-10 version is shown for example purposes only). Where adjustment is required, offset error must be adjusted before full-scale error. This is achieved by trimming the offset of the op amp driving the analog input of the AD7862 while the input voltage is a 1/2 LSB below analog ground. The trim procedure is as follows: apply a voltage of -2.44 mV (-1/2 LSB) at VA1 (see Figure 4) and adjust the op amp offset voltage until the ADC output code flickers between 1111 1111 1111 and 0000 0000 0000.
INPUT RANGE = 10V V1 R1 10k R2 500 R4 R3 10k 10k R5 10k VA1
Analog Inputl +FSR/2 - 1 LSB +FSR/2 - 2 LSBs +FSR/2 - 3 LSBs GND + 1 LSB GND GND - 1 LSB -FSR/2 + 3 LSBs -FSR/2 + 2 LSBs -FSR/2 + 1 LSB
2
Digital Output Code Transition 011 . . . 110 to 011 . . . 111 011 . . . 101 to 011 . . . 110 011 . . . 100 to 011 . . . 101 000 . . . 000 to 000 . . . 001 111 . . . 111 to 000 . . . 000 111 . . . 110 to 111 . . . 111 100 . . . 010 to 100 . . . 011 100 . . . 001 to 100 . . . 010 100 . . . 000 to 100 . . . 001
AD7862*
NOTES 1 FSR is full-scale range = 20 V (AD7862-10) and = 5 V (AD7862-3) with REF IN = +2.5 V. 2 1 LSB = FSR/4096 = 4.883 mV (AD7862-10) and 1.22 mV (AD7862-3) with REF IN = +2.5 V.
AGND
*ADDITIONAL PINS OMITTED FOR CLARITY
The analog input section for the AD7862-2 contains no biasing resistors, and the VAX/BX pin drives the input to the multiplexer and track/hold amplifier circuitry directly. The analog input range is 0 V to +2.5 V into a high impedance stage with an input current of less than 500 nA. This input is benign with no dynamic charging currents. Once again, the designed code transitions occur on successive integer LSB values. Output coding is straight (natural) binary with 1 LSB = FS/4096 = 2.5 V/4096 = 0.61 mV. Table II shows the ideal input/output transfer function for the AD7862-2.
Table II. Ideal Input/Output Code Table for the AD7862-2
Figure 4. Full-Scale Adjust Circuit
Gain error can be adjusted at either the first code transition (ADC negative full scale) or the last code transition (ADC positive full scale). The trim procedures for both cases are as follows:
Positive Full-Scale Adjust
Apply a voltage of +9.9927 V (FS/2 - 3/2 LSBs) at VA1. Adjust R2 until the ADC output code flickers between 0111 1111 1110 and 0111 1111 1111.
Negative Full-Scale Adjust
Analog Input1 +FSR - 1 LSB2 +FSR - 2 LSB +FSR - 3 LSB GND + 3 LSB GND + 2 LSB GND + 1 LSB
Digital Output Code Transition 111 . . . 110 to 111 . . . 111 111 . . . 101 to 111 . . . 110 111 . . . 100 to 111 . . . 101 000 . . . 010 to 000 . . . 011 000 . . . 001 to 000 . . . 010 000 . . . 000 to 000 . . . 001
Apply a voltage of -9.9976 V (-FS + 1/2 LSB) at VA1 and adjust R2 until the ADC output code flickers between 1000 0000 0000 and 1000 0000 0001. An alternative scheme for adjusting full-scale error in systems that use an external reference is to adjust the voltage at the VREF pin until the full-scale error for any of the channels is adjusted out. The good full-scale matching of the channels will ensure small full-scale errors on the other channels.
TIMING AND CONTROL
NOTES 1 FSR is full-scale range and is 2.5 V for AD7862-2 with VREF = +2.5 V. 2 1 LSB = FSR/4096 and is 0.61 mV for AD7862-2 with VREF = +2.5 V.
OFFSET AND FULL-SCALE ADJUSTMENT
In most digital signal processing (DSP) applications, offset and full-scale errors have little or no effect on system performance. Offset error can always be eliminated in the analog domain by ac coupling. Full-scale error effect is linear and does not cause problems as long as the input signal is within the full dynamic range of the ADC. Invariably, some applications will require the input signal to span the full analog input dynamic range. In such
Figure 5a shows the timing and control sequence required to obtain optimum performance (Mode 1) from the AD7862. In the sequence shown, a conversion is initiated on the falling edge of CONVST. This places both track/holds into hold simultaneously, and new data from this conversion is available in the output register of the AD7862 3.6 s later. The BUSY signal indicates the end of conversion, and at this time the conversion results for both inputs are available to be read. A second conversion is then initiated. If the multiplexer select A0 is low, the first and second read pulses after the first conversion accesses the result from channel A (VA1 and VA2 respectively). The third REV. 0
-8-
AD7862
400ns 300ns CONVST
t3
BUSY
A0
tCONV = 3.6s
CS
t1
RD
t2 t4
t7
t5
DATA VA1
t6
VA2 VB1 VB2
Figure 5a. Mode 1 Timing Operation Diagram for High Sampling Performance
and fourth read pulses, after the second conversion and A0 high, access the result from Channel B (VB1 and VB2 respectively). A0's state can be changed any time after the CONVST goes high, i.e., track/holds into hold, and 400 ns prior to the next falling edge of CONVST. Data is read from the part via a 12-bit parallel data bus with standard CS and RD signal, i.e., the read operation consists of a negative going pulse on the CS pin combined with two negative going pulses on the RD pin (while the CS is low), accessing the two 12-bit results. Once the read operation has taken place, a further 300 ns should be allowed before the next falling edge of CONVST to optimize the settling of the track/hold amplifier before the next conversion is initiated. With the internal clock frequency at its maximum (3.7 MHz--not accessible externally), the achievable throughput rate for the part is 3.6 s (conversion time) plus 100 ns (read time) plus 0.3 s (acquisition time). This results in a minimum throughput time of 4 s (equivalent to a throughput rate of 250 kHz).
Read Options
CS
RD
DATA
VA1
VA2
VA1
Figure 5c. Read Option B
A0
CS
Apart from the read operation described above and displayed in Figure 5a, other CS and RD combinations can result in different channels/inputs being read in different combinations. Suitable combinations are shown in Figures 5b through 5d.
RD
DATA
VA1
VB1
Figure 5d. Read Option C
CS
OPERATING MODES Mode 1 Operation (High Sampling Performance)
RD
DATA
VA1
VA2
Figure 5b. Read Option A
The timing diagram in Figure 5a is for optimum performance in operating mode 1 where the falling edge of CONVST starts conversion and puts the track/hold amplifiers into their hold mode. This falling edge of CONVST also causes the BUSY signal to go high to indicate that a conversion is taking place. The BUSY signal goes low when the conversion is complete, which is 3.6 s max after the falling edge of CONVST, and new data from this conversion is available in the output latch of the AD7862. A read operation accesses this data. If the multiplexer select A0 is low, the first and second read pulses after the first conversion access the result from Channel A (VA1 and VA2
REV. 0
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AD7862
respectively). The third and fourth read pulses, after the second conversion and A0 high, access the result from Channel B (VB1 and VB2 respectively). Data is read from the part via a 12-bit parallel data bus with standard CS and RD signals. This data read operation consists of negative going pulse on the CS pin combined with a negative going pulse on the RD pin; this repeated twice will access the two 12-bit results. For the fastest throughput rate (with an internal clock of 3.7 MHz), the read operation will take 100 ns. The read operation must be complete at least 300 ns before the falling edge of the next CONVST, and this gives a total time of 4 s for the full throughput time (equivalent to 250 kHz). This mode of operation should be used for high sampling applications.
Mode 2 Operation (Auto Sleep After Conversion)
because the track/hold amplifiers go into their hold mode on the falling edge of CONVST, and the conversion will not be complete for a further 3.6 s. In this case the BUSY will be the best indicator for when the conversion is complete. Even though the part is in sleep mode, data can still be read from the part. The read operation is identical to Mode 1 operation and must also be complete at least 300 ns before the falling edge of the next CONVST to allow the track/hold amplifiers to have enough time to settle. This mode is very useful when the part is converting at a slow rate, as the power consumption will be significantly reduced from that of Mode 1 operation.
DYNAMIC SPECIFICATIONS
The timing diagram in Figure 6 is for optimum performance in Operating Mode 2 where the part automatically goes into sleep mode once BUSY goes low after conversion and "wakes-up" before the next conversion takes place. This is achieved by keeping CONVST low at the end of the second conversion, whereas it was high at the end of the second conversion for Mode 1 operation. The operation shown in Figure 6 shows how to access data from both Channels A and B followed by the Auto Sleep mode. One can also setup the timing to access data from Channel A only or Channel B only (see Read Options section on previous page) and then go into Auto-Sleep mode. The rising edge of CONVST "wakes-up" the part. This wake-up time is 2.5 s when using an external reference and 5 ms when using the internal reference at which point the Track/Hold amplifier's go into their hold mode, provided the CONVST has gone low. The conversion takes 3.6 s after this, giving a total of 6 s (external reference, 5.0035 ms for internal reference) from the rising edge of CONVST to the conversion being complete, which is indicated by the BUSY going low. Note that since the wake-up time from the rising edge of CONVST is 2.5 s, if the CONVST pulse width is greater than 2.5 s, the conversion will take more than the 6 s (2.5 s wake-up time + 3.6 s conversion time) shown in the diagram from the rising edge of CONVST. This is
400ns 300ns CONVST
The AD7862 is specified and 100% tested for dynamic performance specifications as well as traditional dc specifications such as Integral and Differential Nonlinearity. These ac specifications are required for the signal processing applications such as phased array sonar, adaptive filters and spectrum analysis. These applications require information on the ADC's effect on the spectral content of the input signal. Hence, the parameters for which the AD7862 is specified include SNR, harmonic distortion, intermodulation distortion and peak harmonics. These terms are discussed in more detail in the following sections.
Signal-to-Noise Ratio (SNR)
SNR is the measured signal-to-noise ratio at the output of the ADC. The signal is the rms magnitude of the fundamental. Noise is the rms sum of all the nonfundamental signals up to half the sampling frequency (fS/2) excluding dc. SNR is dependent upon the number of quantization levels used in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to noise ratio for a sine wave input is given by SNR = (6.02N + 1.76) dB where N is the number of bits. Thus for an ideal 12-bit converter, SNR = 74 dB.
2.5s*/5ms** WAKE-UP TIME
(1)
t3
BUSY
t3
tCONV = 3.5s
A0
tCONV = 3.6s
CS
RD
DATA
VA1
VA2
VB1
VB2
**WHEN USING AN EXTERNAL REFERENCE, WAKE-UP TIME = 2.5s **WHEN USING AN INTERNAL REFERENCE, WAKE-UP TIME = 5ms
Figure 6. Mode 2 Timing Where Automatic Sleep Function Is Initiated
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Figure 7 shows a histogram plot for 8192 conversions of a dc input using the AD7862 with 5 V supply. The analog input was set at the center of a code transition. It can be seen that all the codes appear in the one output bin indicating very good noise performance from the ADC.
9000 8000 7000 6000 5000 4000 3000 2000 1000 0 746
-0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 10k 30k 50k 70k 90k 100k 12.2k FSAMPLE = 245760 FIN = 10kHz SNR = -72.95dB THD = -89.99dB
Figure 9. AD7862 FFT Plot
Effective Number of Bits
747 748 749 750 751 752 753 754 755 756
Figure 7. Histogram of 8192 Conversions of a DC Input
The formula given in Equation 1 relates the SNR to the number of bits. Rewriting the formula, as in Equation 2, it is possible to get a measure of performance expressed in effective number of bits (N).
N= SNR - 1.76 6.02
The same data is presented in Figure 8 as in Figure 7 except that in this case the output data read for the device occurs during conversion. This has the effect of injecting noise onto the die while bit decisions are being made and this increases the noise generated by the AD7862. The histogram plot for 8192 conversions of the same dc input now shows a larger spread of codes. This effect will vary depending on where the serial clock edges appear with respect to the bit trials of the conversion process. It is possible to achieve the same level of performance when reading during conversion as when reading after conversion depending on the relationship of the serial clock edges to the bit trial points. The output spectrum from the ADC is evaluated by applying a sine wave signal of very low distortion to the VAX/BX input that is sampled at a 245.76 kHz sampling rate. A Fast Fourier Transform (FFT) plot is generated from which the SNR data can be obtained. Figure 9 shows a typical 2048 point FFT plot of the AD7862 with an input signal of 10 kHz and a sampling frequency of 245.76 kHz. The SNR obtained from this graph is 72.95 dB. It should be noted that the harmonics are taken into account when calculating the SNR.
7000
(2)
The effective number of bits for a device can be calculated directly from its measured SNR. Figure 10 shows a typical plot of effective number of bits versus frequency for an AD7862BN with a sampling frequency of 245.76 kHz. The effective number of bits typically falls between 11.6 and 10.6 corresponding to SNR figures of 71.59 dB and 65.57 dB.
12.0 11.8 11.6 11.4
ENOB
11.2 11.0 10.8 10.6 10.4 10.2 0
200
6000 5000 4000
400 600 FREQUENCY - kHz
800
1000
Figure 10. Effective Numbers of Bits vs. Frequency
Total Harmonic Distortion (THD)
3000 2000 1000 0 745
Total Harmonic Distortion (THD) is the ratio of the rms sum of harmonics to the rms value of the fundamental. For the AD7862, THD is defined as
THD ( dB ) = 20 log
746 747 748 749 750 751 752 753 754 755
2 2 2 2 V2 +V3 +V4 +V5
V1
Figure 8. Histogram of the 8192 Conversions with Read During Conversion
where V1 is the rms amplitude of the fundamental and V2, V3, V4 and V5 are the rms amplitudes of the second through the sixth harmonic. The THD is also derived from the FFT plot of the ADC output spectrum. -11-
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AD7862
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3 . . ., etc. Intermodulation terms are those for which neither m or n are equal to zero. For example, the second order terms include (fa + fb) and (fa - fb) while the third order terms include (2 fa + fb), (2 fa - fb), (fa + 2 fb) and (fa - 2 fb). Using the CCIF standard where two input frequencies near the top end of the input bandwidth are used, the second and third order terms are of different significance. The second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. As a result, the second and third order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in dBs. In this case the input consists of two, equal amplitude, low distortion sine waves. Figure 11 shows a typical IMD plot for the AD7862.
-0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 IMD: 2ND ORDER TERM -88.44 dB 3RD ORDER TERM -66.20 dB INPUT FREQUENCIES F1 = 50010 Hz F2 = 49110 Hz FSAMPLE = 245760 Hz SNR = -60.62dB THD = -89.22dB
where INL(i) is the integral linearity at code i. V(fS) and V(o) are the estimated full-scale and offset transitions, and V(i) is the estimated transition for the ith code. V(i), the estimated code transition point is derived as follows:
x cum ( i ) V (i ) = - A x Cos N
where A is the peak signal amplitude, N is the number of histogram samples
and cum ( i ) =
LSB 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 FIN = 10 kHz FIN = 245.760 kHz TA = 25C
V (n ) occurrences
n =0
i
0
10k
30k
50k
70k
90k
100k 12.3k
Figure 12. AD7862 AC INL Plot
Power Considerations
Figure 11. AD7862 IMD Plot
Peak Harmonic or Spurious Noise
Harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification will be determined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor, the peak will be a noise peak.
AC Linearity Plot
In the automatic power-down mode the part may be operated at a sample rate that is considerably less than 200 kHz. In this case, the power consumption will be reduced and will depend on the sample rate. Figure 13 shows a graph of the power consumption versus sampling rates from 100 Hz to 90 kHz in the automatic power-down mode. The conditions are 5 V supply 25C, and the data was read after conversion.
40 35 30
When a sine wave of specified frequency is applied to the VIN input of the AD7862, and several million samples are taken, a histogram showing the frequency of occurrence of each of the 4096 ADC codes can be generated. From this histogram data, it is possible to generate an ac integral linearity plot as shown in Figure 12. This shows very good integral linearity performance from the AD7862 at an input frequency of 10 kHz. The absence of large spikes in the plot shows good differential linearity. Simplified versions of the formulas used are outlined below.
V ( i ) - V ( o ) x 4096 INL(i ) = V ( f S ) - V (o)
POWER - mW
25 20 15 10 5 0 0.1
(
) - i

10
20
30 40 50 60 FREQUENCY - kHz
70
80
90
Figure 13. Power vs. Sample Rate in Auto Power-Down Mode REV. 0 -12-
AD7862
MICROPROCESSOR INTERFACING
OPTIONAL PA2 ADDRESS BUS PA0 CONVST ADDR DECODE MEN EN A0 CS
The AD7862 high speed bus timing allows direct interfacing to DSP processors as well as modern 16-bit microprocessors. Suitable microprocessor interfaces are shown in Figures 14 through 18.
AD7862-ADSP-2100 Interface
Figure 14 shows an interface between the AD7862 and the ADSP-2100. The CONVST signal can be supplied from the ADSP-2100 or from an external source. The AD7862 BUSY line provides an interrupt to the ADSP-2100 when conversion is completed on all four channels. The four conversion results can then be read from the AD7862 using four successive reads to the same memory address. The following instruction reads one of the four results (this instruction is repeated four times to read all four results in sequence): MR0 = DM(ADC) where MR0 is the ADSP-2100 MR0 register, and ADC is the AD7862 address.
DMA13 ADDRESS BUS DMA0 CONVST ADDR DECODE DMS EN CS A0 OPTIONAL
TMS32010
AD7862*
INT DEN
BUSY RD DB11 DB0
D15 DATA BUS D0 * ADDITIONAL PINS OMITTED FOR CLARITY
Figure 15. AD7862-TMS32010 Interface
AD7862-TMS320C25 Interface
ADSP-2100 (ADSP-2101/ ADSP-2102)
IRQn DMRD (RD)
AD7862*
BUSY RD DB11 DB0
Figure 16 shows an interface between the AD7862 and the TMS320C25. As with the two previous interfaces, conversion can be initiated from the TMS320C25 or from an external source, and the processor is interrupted when the conversion sequence is completed. The TMS320C25 does not have a separate RD output to drive the AD7862 RD input directly. This has to be generated from the processor STRB and R/W outputs with the addition of some logic gates. The RD signal is OR-gated with the MSC signal to provide the one WAIT state required in the read cycle for correct interface timing. Conversion results are read from the AD7862 using the following instruction: IN D,ADC where D is Data Memory address and ADC is the AD7862 address.
OPTIONAL A15 ADDRESS BUS A0
DMD15 DATA BUS DMD0 * ADDITIONAL PINS OMITTED FOR CLARITY
Figure 14. AD7862-ADSP-2100 Interface
AD7862-ADSP-2101/ADSP-2102 INTERFACE
The interface outlined in Figure 14 also forms the basis for an interface between the AD7862 and the ADSP-2101/ADSP-2102. The READ line of the ADSP-2101/ADSP-2102 is labeled RD. In this interface, the RD pulse width of the processor can be programmed using the Data Memory Wait State Control Register. The instruction used to read one of the four results is outlined for the ADSP-2100.
AD7862-TMS32010 Interface
ADDR DECODE IS EN
CONVST A0 CS
TMS320C25
INTn STRB R/W READY MSC
AD7862*
BUSY RD
An interface between the AD7862 and the TMS32010 is shown in Figure 15. Once again, the CONVST signal can be supplied from the TMS32010 or from an external source, and the TMS32010 is interrupted when both conversions have been completed. The following instruction is used to read the conversion results from the AD7862: IN D,ADC where D is Data Memory address, and ADC is the AD7862 address.
DB11 DB0
D15 DATA BUS D0 *ADDITIONAL PINS OMITTED FOR CLARITY
Figure 16. AD7862-TMS320C25 Interface
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AD7862
Some applications may require that the conversion be initiated by the microprocessor rather than an external timer. One option is to decode the AD7862 CONVST from the address bus so that a write operation starts a conversion. Data is read at the end of the conversion sequence as before. Figure 18 shows an example of initiating conversion using this method. Note that for all interfaces, it is preferred that a read operation not be attempted during conversion.
AD7862-MC68000 Interface
A15 ADDRESS BUS A1
80C196
ADDR DECODE
A0 CS
AD7862*
WR RD CONVST RD
An interface between the AD7862 and the MC68000 is shown in Figure 17. As before, conversion can be supplied from the MC68000 or from an external source. The AD7862 BUSY line can be used to interrupt the processor or, alternatively, software delays can ensure that conversion has been completed before a read to the AD7862 is attempted. Because of the nature of its interrupts, the 68000 requires additional logic (not shown in Figure 18) to allow it to be interrupted correctly. For further information on 68000 interrupts, consult the 68000 user's manual. The MC68000 AS and R/W outputs are used to generate a separate RD input signal for the AD7862. CS is used to drive the 68000 DTACK input to allow the processor to execute a normal read operation to the AD7862. The conversion results are read using the following 68000 instruction: MOVE.W ADC,D0 where D0 is the 68000 D0 register, and ADC is the AD7862 address.
OPTIONAL A15 ADDRESS BUS A0
DB11 DB0
D15 ADDRESS/DATA BUS D0 *ADDITIONAL PINS OMITTED FOR CLARITY
Figure 18. AD7862-8086 Interface
Vector Motor Control
The current drawn by a motor can be split into two components: one produces torque, and the other produces magnetic flux. For optimal performance of the motor, these two components should be controlled independently. In conventional methods of controlling a three-phase motor, the current (or voltage) supplied to the motor and the frequency of the drive are the basic control variables; however, both the torque and flux are functions of current (or voltage) and frequency. This coupling effect can reduce the performance of the motor because, if the torque is increased by increasing the frequency, for example, the flux tends to decrease. Vector control of an ac motor involves controlling phase in addition to drive and current frequency. Controlling the phase of the motor requires feedback information on the position of the rotor relative to the rotating magnetic field in the motor. Using this information, a vector controller mathematically transforms the three phase drive currents into separate torque and flux components. The AD7862, with its four-channel simultaneous sampling capability, is ideally suited for use in vector motor control applications. A block diagram of a vector motor control application using the AD7862 is shown in Figure 19. The position of the field is derived by determining the current in each phase of the motor. Only two phase currents need to be measured because the third can be calculated if two phases are known. VA1 and VA2 of the AD7862 are used to digitize this information. Simultaneous sampling is critical to maintain the relative phase information between the two channels. A current sensing isolation amplifier, transformer or Hall effect sensor is used between the motor and the AD7862. Rotor information is obtained by measuring the voltage from two of the inputs to the motor. VB1 and VB2 of the AD7862 are used to obtain this information. Once again, the relative phase of the two channels is important. A DSP microprocessor is used to perform the mathematical transformations and control loop calculations on the information fed back by the AD7862.
ADDR DECODE
A0 CS
CONVST
MC68000
DTACK AS R/W
EN
AD7862*
RD
DB11 DB0 D15 DATA BUS D0 *ADDITIONAL PINS OMITTED FOR CLARITY
Figure 17. AD7862-MC68000 Interface
AD7862-80C196 Interface
Figure 18 shows an interface between the AD7862 and the 80C196 microprocessor. Here, the microprocessor initiates conversion. This is achieved by gating the 80C196 WR signal with a decoded address output (different to the AD7862 CS address). The AD7862 BUSY line is used to interrupt the microprocessor when the conversion sequence is completed.
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AD7862
DSP MICROPROCESSOR TORQUE & FLUX CONTROL LOOP CALCULATIONS & TWO TO THREE PHASE INFORMATION TORQUE SETPOINT DAC DAC DAC DRIVE CIRCUITRY IB VB VA IA
3 PHASE MOTOR
IC
of AD7862 number 1 is used to drive the reference input of all other AD7862s in the circuit shown in Figure 20. One VREF pin can drive several AD7862 REF IN pins. Alternatively, an external or system reference can be used to drive all VREF inputs. A common reference ensures good full-scale tracking between all channels.
VA1
ISOLATION AMPLIFIERS FLUX SETPOINT TRANSFORMATION TO TORQUE & FLUX CURRENT COMPONENTS VA1 VA2
VB1 VA2 VB2 VREF
RD
RD
AD7862(1)
CS
AD7862*
VB1 VB2 *ADDITIONAL PINS OMITTED FOR CLARITY VOLTAGE ATTENUATORS
VA1 VB1 VA2 RD
AD7862(2)
CS REF IN
ADDRESS DECODE ADDRESS
Figure 19. Vector Motor Control Using the AD7862
MULTIPLE AD7862S
VB2
Figure 20 shows a system where a number of AD7862s can be configured to handle multiple input channels. This type of configuration is common in applications such as sonar, radar, etc. The AD7862 is specified with typical limits on aperture delay. This means that the user knows the difference in the sampling instant between all channels. This allows the user to maintain relative phase information between the different channels. A common read signal from the microprocessor drives the RD input of all AD7862s. Each AD7862 is designated a unique address selected by the address decoder. The reference output
REF IN VA1 VB1 VA2 VB2 CS RD
AD7862(n)
Figure 20. Multiple AD7862s in Multichannel System
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AD7862
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Pin Plastic DIP (N-28)
1.565 (39.70) 1.380 (35.10)
28 15
28
28-Pin Small Outline Package (R-28)
0.7125 (18.10) 0.6969 (17.70)
15
1
14
PIN 1 0.250 (6.35) MAX 0.200 (5.05) 0.022 (0.558) 0.125 (3.18) 0.014 (0.356)
0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN 0.100 (2.54) BSC 0.070 (1.77) MAX SEATING PLANE
0.625 (15.87) 0.600 (15.24)
0.195 (4.95) 0.125 (3.18)
1
14
PIN 1
0.015 (0.381) 0.008 (0.204)
0.1043 (2.65) 0.0926 (2.35)
0.4193 (10.65) 0.3937 (10.00)
0.2992 (7.60) 0.2914 (7.40)
0.580 (14.73) 0.485 (12.32)
0.0291 (0.74) x 45 0.0098 (0.25)
0.0118 (0.30) 0.0040 (0.10)
0.0500 (1.27) BSC
8 0.0192 (0.49) 0 SEATING 0.0125 (0.32) 0.0138 (0.35) PLANE 0.0091 (0.23)
0.0500 (1.27) 0.0157 (0.40)
28-Pin Cerdip (Q-28)
0.005 (0.13) MIN
28
28-Pin Shrink Small Outline Package (RS-28)
0.407 (10.34) 0.397 (10.08)
0.100 (2.54) MAX
15
1
14
PIN 1 1.490 (37.85) MAX 0.225 (5.72) MAX
0.015 (0.38) MIN 0.150 (3.81) MIN 15 0
0.620 (15.75) 0.590 (14.99)
0.311 (7.9) 0.301 (7.64)
1
14
0.018 (0.46) 0.008 (0.20)
0.200 (5.08) 0.026 (0.66) 0.110 (2.79) 0.070 (1.78) SEATING 0.125 (3.18) 0.014 (0.36) 0.090 (2.29) 0.030 (0.76) PLANE
0.078 (1.98) PIN 1 0.068 (1.73)
0.07 (1.79) 0.066 (1.67)
0.212 (5.38) 0.205 (5.21)
0.610 (15.49) 0.500 (12.70)
28
15
0.008 (0.203) 0.0256 (0.65) 0.002 (0.050) BSC
0.015 (0.38) 0.010 (0.25)
SEATING 0.009 (0.229) PLANE 0.005 (0.127)
8 0
0.03 (0.762) 0.022 (0.558)
-16-
REV. 0
PRINTED IN U.S.A.
C2211-12-10/96

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